3D Plus
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
7
Ending by 2030
Feb 2028
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Dec 25, 2026The maintenance fee for Method of miniaturized chip on chip interconnection of a 3D electronic module (US 10,332,863) comes due Dec 25, 2026. Unpaid by Jun 25, 2027, it lapses early.
- 1 fee due Feb 18, 2027The maintenance fee for Method for producing reconstituted wafers with support of the chips during their encapsulation (US 9,111,688) comes due Feb 18, 2027. Unpaid by Aug 18, 2027, it lapses early.
- 1 fee due May 5, 2027The maintenance fee for 3D imaging optoelectronic module (US 10,466,097) comes due May 5, 2027. Unpaid by Nov 5, 2027, it lapses early.
Recent changes
- 1 term has ended since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 7,877,874 | Process for the collective fabrication of 3D electronic modules In force · From the USPTO record | In force | From the USPTO record | |
| US 7,951,649 | Process for the collective fabrication of 3D electronic modules In force · From the USPTO record | In force | From the USPTO record | |
| US 8,136,237 | Method of interconnecting electronic wafers In force · From the USPTO record | In force | From the USPTO record | |
| US 8,243,468 | Low-thickness electronic module comprising a stack of electronic packages provided with connection balls In force · From the USPTO record | In force | From the USPTO record | |
| US 8,264,853 | 3D electronic module In force · From the USPTO record | In force | From the USPTO record | |
| US 8,546,190 | Method for positioning chips during the production of a reconstituted wafer In force · From the USPTO record | In force | From the USPTO record | |
| US 8,359,740 | Process for the wafer-scale fabrication of electronic modules for surface mounting In force · From the USPTO record | In force | From the USPTO record | |
| US 8,567,051 | Process for the vertical interconnection of 3D electronic modules by vias In force · From the USPTO record | In force | From the USPTO record | |
| US 9,111,688 | Method for producing reconstituted wafers with support of the chips during their encapsulation In force · From the USPTO record | In force | From the USPTO record | |
| US 8,716,036 | Method for collective fabrication of 3D electronic modules comprising only validated PCBs In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 19: 2 lapsed for an unpaid fee · 4 ended at full term. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
2 pending · 1 abandoned · 3 no status recorded