Adeia Semiconductor Inc.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
Previously recorded as Xcelsis Corporation (to 2022)
0
Ending by 2030
Jan 2036
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Dec 27, 2026The maintenance fee for Transistor level interconnection methodologies utilizing 3D interconnects (US 11,688,776) comes due Dec 27, 2026. Unpaid by Jun 28, 2027, it lapses early.
- 2 fees due Feb 22 to 28, 2027 · next Feb 22
- 1 fee due Mar 5, 2027The maintenance fee for Segmented LED with Embedded Transistors (US 11,749,790) comes due Mar 5, 2027. Unpaid by Sep 7, 2027, it lapses early.
- 1 fee due Apr 17, 2027The maintenance fee for Three dimensional circuit implementing machine trained network (US 11,790,219) comes due Apr 17, 2027. Unpaid by Oct 18, 2027, it lapses early.
- 1 fee due May 21, 2027The maintenance fee for 3D chip sharing data bus (US 11,824,042) comes due May 21, 2027. Unpaid by Nov 22, 2027, it lapses early.
- 1 fee due Jun 30, 2027The maintenance fee for Direct-Bonded Native Interconnects and Active Base Die (US 10,522,352) comes due Jun 30, 2027. Unpaid by Jan 3, 2028, it lapses early.
- 2 fees due Jul 2 to 23, 2027 · next Jul 2
- 5 fees due Aug 6 to 27, 2027 · next Aug 6
- 8 fees due Sep 3 to 30, 2027 · next Sep 3
- 1 fee due Oct 16, 2027The maintenance fee for Monolithic Segmented LED Array Architecture With Islanded Epitaxial Growth (US 11,961,875) comes due Oct 16, 2027. Unpaid by Apr 17, 2028, it lapses early.
Recent changes
- 2 of the patents on this record were granted since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 11,289,333 | Direct-Bonded Native Interconnects And Active Base Die In force · High confidence | In force | High confidence | |
| US 10,026,864 | Package-less LED Assembly and Method In force · High confidence | In force | High confidence | |
| US 10,580,735 | Stacked IC structure with system level wiring on multiple sides of the IC die In force · From the USPTO record | In force | From the USPTO record | |
| US 10,580,757 | Face-to-face mounted IC dies with orthogonal top interconnect layers In force · From the USPTO record | In force | From the USPTO record | |
| US 10,586,786 | 3D chip sharing clock interconnect layer In force · From the USPTO record | In force | From the USPTO record | |
| US 10,593,667 | 3D chip with shielded clock lines In force · From the USPTO record | In force | From the USPTO record | |
| US 10,600,691 | 3D chip sharing power interconnect layer In force · From the USPTO record | In force | From the USPTO record | |
| US 10,600,735 | 3D chip sharing data bus In force · From the USPTO record | In force | From the USPTO record | |
| US 10,600,780 | 3D chip sharing data bus circuit In force · From the USPTO record | In force | From the USPTO record | |
| US 10,672,663 | 3D Chip Sharing Power Circuit In force · Medium confidence | In force | Medium confidence |
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
4 pending · 5 no status recorded