Adeia Semiconductor Technologies LLC
1 more in force is now held by another company
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
Previously recorded as Invensas Corporation (to 2022)
56
Ending by 2030
Dec 2026
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 2 fees due Nov 26 to 28, 2026 · next Nov 26
- 9 fees due Dec 11 to 30, 2026 · next Dec 11
- 9 fees due Jan 7 to 28, 2027 · next Jan 7
- 8 fees due Feb 1 to 27, 2027 · next Feb 1
- 11 fees due Mar 1 to 29, 2027 · next Mar 1
- 12 fees due Apr 1 to 30, 2027 · next Apr 1
- 8 fees due May 5 to 26, 2027 · next May 5
- 7 fees due Jun 5 to 30, 2027 · next Jun 5
- 11 fees due Jul 2 to 28, 2027 · next Jul 2
- 9 fees due Aug 2 to 20, 2027 · next Aug 2
- 16 fees due Sep 8 to 29, 2027 · next Sep 8
- 9 fees due Oct 12 to 30, 2027 · next Oct 12
- 5 fees due Nov 3 to 10, 2027 · next Nov 3
Recent changes
- 4 of the patents on this record were granted since Aug 16, 2026
- 7 terms have ended since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 7,553,759 | Semiconductor Device and Method of Manufacturing a Semiconductor Device In force · High confidence | In force | High confidence | |
| US 7,704,881 | Producing a Covered Through Substrate via Using a Temporary Cap Layer In force · High confidence | In force | High confidence | |
| US 7,888,176 | Stacked Integrated Circuit Assembly In force · High confidence | In force | High confidence | |
| US 7,838,983 | Packaged Semiconductor Device and Method of Manufacturing the Packaged Semiconductor Device In force · Medium confidence | In force | Medium confidence | |
| US 7,964,508 | Dielectric Trenches, Nickel/Tantalum Oxide Structures, and Chemical Mechanical Polishing Techniques In force · High confidence | In force | High confidence | |
| US 8,030,779 | Multi-Layered Metal Interconnection In force · High confidence | In force | High confidence | |
| US 7,605,477 | Stacked Integrated Circuit Assembly In force · High confidence | In force | High confidence | |
| US 7,649,406 | Short-Circuit Charge-Sharing Technique for Integrated Circuit Devices In force · High confidence | In force | High confidence | |
| US 8,239,740 | Circuit and Technique for Reducing Parity Bit-Widths for Check Bit and Syndrome Generation for Data Blocks Through the Use of Additional Check Bits to Increase the Number of Minimum Weighted Codes in the Hamming Code H-Matrix In force · Medium confidence | In force | Medium confidence | |
| US 8,510,641 | Circuit and Technique for Reducing Parity Bit-Widths for Check Bit and Syndrome Generation for Data Blocks Through the Use of Additional Check Bits to Increase the Number of Minimum Weighted Codes in the Hamming Code H-Matrix In force · High confidence | In force | High confidence |
Also on record, not counted in the 507: 1 patent in force now held by others · 31 lapsed for an unpaid fee · 20 ended at full term · 1 past the fee grace period · 4 surrendered on reissue. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
23 pending