Amida Technology Solutions, Inc.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
0
Ending by 2030
Sep 2038
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
No maintenance fee falls due on this company's record before Nov 14, 2027.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
Showing 1 to 8 of 8
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 12,026,250 | Method, system, and apparatus for security assurance, protection, monitoring and analysis of integrated circuits and electronic systems in relation to hardware trojans In force · From the USPTO record | In force | From the USPTO record | |
| US 12,682,049 | Method and System for Insertion of Cybersecurity and Hardware Assurance Instruments Within Integrated Circuits and Electronic Systems Using Multi-Stage Hardware Marking In force · Low confidence | In force | Low confidence | |
| US 11,681,795 | Method, system and apparatus for security assurance, protection, monitoring and analysis of integrated circuits and electronic systems in relation to hardware trojans In force · From the USPTO record | In force | From the USPTO record | |
| US 10,909,284 | Method and system for selection of location for placement of trojans, triggers and instruments within integrated circuits and electronic systems using weighted controllability and observability analysis In force · From the USPTO record | In force | From the USPTO record | |
| US 11,157,619 | Method and system for selection of location for placement of trojans, triggers and instruments within integrated circuits and electronic systems using contributory operation analysis In force · From the USPTO record | In force | From the USPTO record | |
| US 12,210,618 | Method and system for insertion of cybersecurity and hardware assurance instruments within intergrated circuits and electronic systems using multi-stage hardware marking In force · From the USPTO record | In force | From the USPTO record | |
| US 11,277,419 | Method, system, and apparatus for verification of operation using GPS receiver input within integrated circuits and electronic systems using an operation navigation system In force · From the USPTO record | In force | From the USPTO record | |
| US 11,736,501 | Method, System, and Apparatus for Security Assurance, Protection, Monitoring and Analysis of Integrated Circuits and Electronic Systems Using Machine Learning Instruments and Machine Learning Analysis In force · High confidence | In force | High confidence |
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
2 no status recorded