Anapass Inc.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
8
Ending by 2030
May 2027
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Feb 13, 2027The maintenance fee for Frame rate detection method and frame rate conversion method (US 10,382,718) comes due Feb 13, 2027. Unpaid by Aug 13, 2027, it lapses early.
- 5 fees due Mar 15 to 29, 2027 · next Mar 15
- 2 fees due Apr 15 to 20, 2027 · next Apr 15
- 1 fee due May 10, 2027The maintenance fee for Apparatus and method for detecting adjacent object and method of driving electronic device (US 9,182,867) comes due May 10, 2027. Unpaid by Nov 10, 2027, it lapses early.
- 2 fees due Jun 24 to 30, 2027 · next Jun 24
- 1 fee due Sep 1, 2027The maintenance fee for Method of detecting touch and apparatus for detecting touch using the same (US 9,274,663) comes due Sep 1, 2027. Unpaid by Mar 1, 2028, it lapses early.
- 1 fee due Nov 5, 2027The maintenance fee for Method of driving display, display device, and source driver (US 10,643,551) comes due Nov 5, 2027. Unpaid by May 5, 2028, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 7,969,338 | Decoding circuit for flat panel display In force · From the USPTO record | In force | From the USPTO record | |
| US 8,149,253 | Display, timing controller and data driver for transmitting serialized multi-level data signal In force · From the USPTO record | In force | From the USPTO record | |
| US 7,812,656 | Data driver circuit and delay-locked loop In force · From the USPTO record | In force | From the USPTO record | |
| US 8,074,125 | Apparatus and method for transmitting and receiving data bits In force · From the USPTO record | In force | From the USPTO record | |
| US 8,094,147 | Display device and method for transmitting clock signal during blank period In force · From the USPTO record | In force | From the USPTO record | |
| US 8,031,189 | Data driver circuit and delay-locked loop circuit In force · From the USPTO record | In force | From the USPTO record | |
| US 9,934,712 | Display, timing controller and column driver integrated circuit using clock embedded multi-level signaling In force · From the USPTO record | In force | From the USPTO record | |
| US 8,576,015 | Signal generator In force · From the USPTO record | In force | From the USPTO record | |
| US 8,558,827 | Data driving circuit, display apparatus, and data driving method with reception signal In force · From the USPTO record | In force | From the USPTO record | |
| US 8,547,365 | Display apparatus and method for outputting parallel data signals at different application starting time points In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 46: 4 ended at full term. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
3 pending · 2 no status recorded