Aplus Flash Technology, Inc.
Records under this name other than patents Aplus Flash Technology, Inc. holds now: patents now held by others, patents whose terms have ended, and its applications, pending or abandoned.
Back to Aplus Flash Technology, Inc.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 7,369,438 | Novel Combo Memory Design and Technology for Multiple-Function Java Card, SIM-Card, Bio-Passport and Bio-Id Card Applications Formerly held Term ended Term ended Apr 1, 2026 · High confidence | Term ended | Term ended Apr 1, 2026 | High confidence |
| US 9,666,286 | Self-timed SLC NAND pipeline and concurrent program without verification Lapsed on the fee record Ended May 30, 2025 · From the USPTO record | Lapsed on the fee record | Ended May 30, 2025 | From the USPTO record |
| US 9,613,704 | 2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify Lapsed on the fee record Ended Apr 4, 2025 · From the USPTO record | Lapsed on the fee record | Ended Apr 4, 2025 | From the USPTO record |
| US 7,087,953 | Unified Non-Volatile Memory Device and Method for Integrating nor and NAND-Type Flash Memory and EEPROM Device on a Single Substrate Formerly held Term ended Term ended Jan 21, 2025 · High confidence | Term ended | Term ended Jan 21, 2025 | High confidence |
| US 7,177,190 | Novel Combination Nonvolatile Integrated Memory System Using a Universal Technology Most Suitable for High-Density, High-Flexibility and High-Security SIM-Card, Smart-Card and E-Passport Applications Formerly held Term ended Term ended Jan 15, 2025 · High confidence | Term ended | Term ended Jan 15, 2025 | High confidence |
| US 9,443,578 | NAND array architecture for multiple simultaneous program and read Lapsed on the fee record Ended Sep 13, 2024 · From the USPTO record | Lapsed on the fee record | Ended Sep 13, 2024 | From the USPTO record |
| US 9,443,579 | VSL-based VT-compensation and analog program scheme for NAND array without CSL Lapsed on the fee record Ended Sep 13, 2024 · From the USPTO record | Lapsed on the fee record | Ended Sep 13, 2024 | From the USPTO record |
| US 9,437,306 | NAND array architecture for multiple simutaneous program and read Lapsed on the fee record Ended Sep 6, 2024 · From the USPTO record | Lapsed on the fee record | Ended Sep 6, 2024 | From the USPTO record |
| US 9,293,205 | Multi-task concurrent/pipeline NAND operations on all planes Lapsed on the fee record Ended Mar 22, 2024 · From the USPTO record | Lapsed on the fee record | Ended Mar 22, 2024 | From the USPTO record |
| US 9,263,137 | NAND array architecture for multiple simutaneous program and read Lapsed on the fee record Ended Feb 16, 2024 · From the USPTO record | Lapsed on the fee record | Ended Feb 16, 2024 | From the USPTO record |