Array Cache Technologies LLC
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
0
Ending by 2030
Jan 2034
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Dec 18, 2026The maintenance fee for Systems and methods for coherence in clustered cache hierarchies (US 10,324,861) comes due Dec 18, 2026. Unpaid by Jun 21, 2027, it lapses early.
- 1 fee due Feb 20, 2027The maintenance fee for System and method for event monitoring in cache coherence protocols without explicit invalidations (US 10,387,312) comes due Feb 20, 2027. Unpaid by Aug 20, 2027, it lapses early.
- 1 fee due Jul 7, 2027The maintenance fee for System and method for self-invalidation, self-downgrade cachecoherence protocols (US 10,528,471) comes due Jul 7, 2027. Unpaid by Jan 7, 2028, it lapses early.
- 1 fee due Sep 1, 2027The maintenance fee for System and method for simplifying cache coherence using multiple write policies (US 9,274,960) comes due Sep 1, 2027. Unpaid by Mar 1, 2028, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
Showing 1 to 10 of 10
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 9,274,960 | System and method for simplifying cache coherence using multiple write policies In force · From the USPTO record | In force | From the USPTO record | |
| US 11,237,966 | System and method for event monitoring in cache coherence protocols without explicit invalidations In force · From the USPTO record | In force | From the USPTO record | |
| US 10,387,312 | System and method for event monitoring in cache coherence protocols without explicit invalidations In force · From the USPTO record | In force | From the USPTO record | |
| US 11,068,410 | Multi-core computer systems with private/shared cache line indicators In force (reinstated) · From the USPTO record | In force (reinstated) | From the USPTO record | |
| US 10,324,861 | Systems and methods for coherence in clustered cache hierarchies In force · From the USPTO record | In force | From the USPTO record | |
| US 10,528,471 | System and method for self-invalidation, self-downgrade cachecoherence protocols In force (reinstated) · From the USPTO record | In force (reinstated) | From the USPTO record | |
| US 11,188,464 | System and method for self-invalidation, self-downgrade cachecoherence protocols In force · From the USPTO record | In force | From the USPTO record | |
| US 11,119,920 | Systems and methods for non-speculative store coalescing and generating atomic write sets using address subsets In force · From the USPTO record | In force | From the USPTO record | |
| US 11,163,576 | Systems and methods for invisible speculative execution In force · From the USPTO record | In force | From the USPTO record | |
| US 11,334,485 | System and method for dynamic enforcement of store atomicity In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 10: 1 lapsed for an unpaid fee. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.