The Patent Finder

Ascale Technologies LLC

21 patents currently held · Updated Nov 14, 2026
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
9
Ending by 2030
Jan 2027
Next term end

When these terms end

Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045

Fee deadlines

Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
  • 1 fee due Nov 26, 2026
    The maintenance fee for Bus Signal Encoded with Data and Clock Signals (US 9,041,564) comes due Nov 26, 2026. Unpaid by May 26, 2027, it lapses early.
  • 2 fees due Jan 21 to 28, 2027 · next Jan 21
  • 1 fee due Mar 22, 2027
    The maintenance fee for Data Processing System with Latency Tolerance Execution (US 9,141,391) comes due Mar 22, 2027. Unpaid by Sep 22, 2027, it lapses early.
  • 1 fee due Apr 20, 2027
    The maintenance fee for Routing Standard Cell-Based Integrated Circuits (US 9,165,102) comes due Apr 20, 2027. Unpaid by Oct 20, 2027, it lapses early.

Which patents, and when each one lapses · Pro

Recent changes

  • 2 terms have ended since Aug 16, 2026

Patents held now

Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
PatentTitleStatus Expires Confidence
US 7,378,993Method and System for Transmitting Data
In force
 · High confidence
In forceHigh confidence
US 7,428,172Concurrent Programming and Program Verification of Floating Gate Transistor
In force
 · High confidence
In forceHigh confidence
US 7,490,266Integrated Circuit and Processing System with Improved Power Source Monitoring and Methods for Use Therewith
In force
 · High confidence
In forceHigh confidence
US 8,223,910Method and Device for Frame Synchronization
In force
 · High confidence
In forceHigh confidence
US 7,640,389Non-Volatile Memory Having a Multiple Block Erase Mode and Method Therefor
In force
 · High confidence
In forceHigh confidence
US 7,616,509Dynamic Voltage Adjustment for Memory
In force
 · High confidence
In forceHigh confidence
US 7,681,106Error Correction Device and Methods Thereof
In force
 · High confidence
In forceHigh confidence
US 7,953,991Processing System and Methods for Use Therewith
In force
 · High confidence
In forceHigh confidence
US 8,739,165Shared Resource Based Thread Scheduling with Affinity And/Or Selectable Criteria
In force
 · High confidence
In forceHigh confidence
US 8,760,136Dynamic Voltage Scaling Interface
In force
 · High confidence
In forceHigh confidence
10 of 21 patents shown.
Pro members see all 21.
Pro members: see all 21 patents
Also on record, not counted in the 21: 2 ended at full term. List them

Sources and methods

Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand. How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
The Patent Finder CompaniesExpirationsCalculatorWatchlistPricing MethodologyCorrectionsLegalPrivacysupport@thepatentfinder.com Updated Nov 14, 2026 · includes USPTO assignment & status data published Nov 14, 2026 and grant & fee data published Nov 10, 2026 (weekly) Part of 137 Finder · © 2026 137 Finder LLC · Sources cited