Axis Semiconductor, Inc.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
3
Ending by 2030
Feb 2029
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Jan 7, 2027The maintenance fee for Hierarchical multi-core processor and method of programming for efficient data processing (US 9,075,768) comes due Jan 7, 2027. Unpaid by Jul 7, 2027, it lapses early.
- 1 fee due Feb 22, 2027The maintenance fee for Computing device with circuit switched memory access (US 11,734,211) comes due Feb 22, 2027. Unpaid by Aug 23, 2027, it lapses early.
- 1 fee due Aug 18, 2027The maintenance fee for Method of synchronizing host and coprocessor operations via FIFO communication (US 10,565,036) comes due Aug 18, 2027. Unpaid by Feb 18, 2028, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
Showing 1 to 8 of 8
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 8,099,583 | Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing In force · From the USPTO record | In force | From the USPTO record | |
| US 8,078,833 | Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions In force · From the USPTO record | In force | From the USPTO record | |
| US 8,181,003 | Instruction set design, control and communication in programmable microprocessor cores and the like In force · From the USPTO record | In force | From the USPTO record | |
| US 8,811,387 | Dynamically reconfigurable hybrid circuit-switched and packet-switched network architecture In force · From the USPTO record | In force | From the USPTO record | |
| US 9,075,768 | Hierarchical multi-core processor and method of programming for efficient data processing In force · From the USPTO record | In force | From the USPTO record | |
| US 10,565,036 | Method of synchronizing host and coprocessor operations via FIFO communication In force · From the USPTO record | In force | From the USPTO record | |
| US 11,734,211 | Computing device with circuit switched memory access In force · From the USPTO record | In force | From the USPTO record | |
| US 11,455,272 | Energy efficient microprocessor with index selected hardware architecture In force · From the USPTO record | In force | From the USPTO record |
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
1 no status recorded