Catlam LLC
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
0
Ending by 2030
May 2034
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Aug 25, 2027The maintenance fee for Method for wafer level packaging (US 10,573,610) comes due Aug 25, 2027. Unpaid by Feb 25, 2028, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 9,631,279 | Methods for forming embedded traces In force · From the USPTO record | In force | From the USPTO record | |
| US 9,674,967 | Via in a printed circuit board In force · From the USPTO record | In force | From the USPTO record | |
| US 9,706,667 | Via in a printed circuit board In force · From the USPTO record | In force | From the USPTO record | |
| US 9,380,700 | Method for forming traces of a printed circuit board In force · From the USPTO record | In force | From the USPTO record | |
| US 9,398,703 | Via in a printed circuit board In force · From the USPTO record | In force | From the USPTO record | |
| US 10,573,610 | Method for wafer level packaging In force · From the USPTO record | In force | From the USPTO record | |
| US 9,706,650 | Catalytic laminate apparatus and method In force · From the USPTO record | In force | From the USPTO record | |
| US 9,942,981 | Circuit board apparatus and method In force · From the USPTO record | In force | From the USPTO record | |
| US 10,306,756 | Circuit board with catalytic adhesive In force · From the USPTO record | In force | From the USPTO record | |
| US 10,806,029 | Catalytic circuit board with traces and vias In force · From the USPTO record | In force | From the USPTO record |
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
1 no status recorded