Clearlogic
Records under this name other than the patents Clearlogic holds now: patents now held by others, patents whose terms have ended, and its applications, pending or abandoned. None of them is counted in the 1 patents it holds.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 6,311,316 | Designing integrated circuit gate arrays using programmable logic device bitstreams Lapsed on the fee record Ended Oct 30, 2013 · From the USPTO record | Lapsed on the fee record | Ended Oct 30, 2013 | From the USPTO record |
| US 6,531,756 | Laser fuse and antifuse structures formed over the active circuitry of an integrated circuit Lapsed on the fee record Ended Mar 11, 2007 · From the USPTO record | Lapsed on the fee record | Ended Mar 11, 2007 | From the USPTO record |
| US 6,486,527 | Vertical fuse structure for integrated circuits containing an exposure window in the layer over the fuse structure to facilitate programming thereafter Lapsed on the fee record Ended Nov 26, 2006 · From the USPTO record | Lapsed on the fee record | Ended Nov 26, 2006 | From the USPTO record |
| US 6,369,437 | Vertical fuse structure for integrated circuits and a method of disconnecting the same Lapsed on the fee record Ended Apr 9, 2006 · From the USPTO record | Lapsed on the fee record | Ended Apr 9, 2006 | From the USPTO record |
| US 6,348,742 | Sacrificial bond pads for laser configured integrated circuits Lapsed on the fee record Ended Feb 19, 2006 · From the USPTO record | Lapsed on the fee record | Ended Feb 19, 2006 | From the USPTO record |
| US 6,346,748 | Electronic circuit structure with photoresist layer that has non-precision openings formed by a laser Lapsed on the fee record Ended Feb 12, 2006 · From the USPTO record | Lapsed on the fee record | Ended Feb 12, 2006 | From the USPTO record |
| US 6,239,480 | Modified lead frame for improved parallelism of a die to package Lapsed on the fee record Ended May 29, 2005 · From the USPTO record | Lapsed on the fee record | Ended May 29, 2005 | From the USPTO record |
| US 6,235,556 | Method of improving parallelism of a die to package using a modified lead frame Lapsed on the fee record Ended May 22, 2005 · From the USPTO record | Lapsed on the fee record | Ended May 22, 2005 | From the USPTO record |
| US 6,228,564 | Method of patterning photoresist using precision and non-precision techniques Lapsed on the fee record Ended May 8, 2005 · From the USPTO record | Lapsed on the fee record | Ended May 8, 2005 | From the USPTO record |
| US 6,225,652 | Vertical laser fuse structure allowing increased packing density Lapsed on the fee record Ended May 1, 2005 · From the USPTO record | Lapsed on the fee record | Ended May 1, 2005 | From the USPTO record |