Coresecure Technologies, LLC

17 patents currently held · Updated Nov 14, 2026

Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.

Ending by 2030

Nov 2028

Next term end

When these terms end

5 yrs10 yrs20 yrs

Held patents by the year their term ends

20262027202820292030203120322033203420352036203720382039204020412042204320442045

Fee deadlines

Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.

1 fee due Feb 18, 2027
The maintenance fee for Cache memory having enhanced performance and security features (US 9,110,816) comes due Feb 18, 2027. Unpaid by Aug 18, 2027, it lapses early.
1 fee due Mar 15, 2027
The maintenance fee for Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor (US 9,134,953) comes due Mar 15, 2027. Unpaid by Sep 15, 2027, it lapses early.
1 fee due Oct 19, 2027
The maintenance fee for Hardware Trust Anchors in Sp-Enabled Processors (US 9,317,708) comes due Oct 19, 2027. Unpaid by Apr 19, 2028, it lapses early.

Which patents, and when each one lapses · Pro

Recent changes

Nothing was recorded against this company's patents in the last 90 days.

Patents held now

Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.

Patent	Title	Status	Expires	Confidence
US 9,134,953	Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor In force Term ends Nov 19, 2028 · High confidence	In force	Term ends Nov 19, 2028	High confidence
US 9,110,816	Cache memory having enhanced performance and security features In force Term ends Dec 8, 2029 · From the USPTO record	In force	Term ends Dec 8, 2029	From the USPTO record
US 9,864,703	Cache memory having enhanced performance and security features In force Term ends Dec 8, 2029 · From the USPTO record	In force	Term ends Dec 8, 2029	From the USPTO record
US 8,943,297	Parallel read functional unit for microprocessors In force Ends no later than Jan 19, 2030 · From the USPTO record	In force	Ends no later than Jan 19, 2030	From the USPTO record
US 9,784,260	System and method for processor-based security In force Ends no later than Jan 19, 2030 · From the USPTO record	In force	Ends no later than Jan 19, 2030	From the USPTO record
US 9,989,043	System and method for processor-based security In force Term ends Jan 19, 2030 · From the USPTO record	In force	Term ends Jan 19, 2030	From the USPTO record
US 8,352,708	Parallel read functional unit for microprocessors In force Term ends Apr 2, 2031 · From the USPTO record	In force	Term ends Apr 2, 2031	From the USPTO record
US 8,738,932	System and method for processor-based security In force Term ends Aug 3, 2031 · From the USPTO record	In force	Term ends Aug 3, 2031	From the USPTO record
US 8,549,208	Cache memory having enhanced performance and security features In force Term ends Sep 6, 2031 · From the USPTO record	In force	Term ends Sep 6, 2031	From the USPTO record
US 9,317,708	Hardware Trust Anchors in Sp-Enabled Processors In force Term ends Aug 14, 2032 · High confidence	In force	Term ends Aug 14, 2032	High confidence

10 of 17 patents shown.

Pro members see all 17.

Pro members: see all 17 patents

Sources and methods

Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand. How this record was built

Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.

Export every term end as CSV · Pro

Published applications

Every application published under this name has become a patent.