Eever Technology, Inc.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
0
Ending by 2030
May 2031
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 2 fees due Feb 6, 2027
- 1 fee due May 26, 2027The maintenance fee for USB Type-C module (US 10,489,325) comes due May 26, 2027. Unpaid by Nov 26, 2027, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 8,359,489 | Frequency calibration circuit for automatically calibrating a frequency generated by an oscillator and method thereof In force · From the USPTO record | In force | From the USPTO record | |
| US 8,605,777 | Circuit for recognizing a beginning and a data rate of data and method thereof In force · From the USPTO record | In force | From the USPTO record | |
| US 8,373,473 | Dual-loop phase lock loop In force · From the USPTO record | In force | From the USPTO record | |
| US 8,330,535 | Equalizer and method of equalizing signals In force · From the USPTO record | In force | From the USPTO record | |
| US 8,473,801 | Method for increasing efficiency of transferring packet of isochronous transfer type and device thereof In force · From the USPTO record | In force | From the USPTO record | |
| US 8,566,501 | Circuit for simultaneously analyzing performance and bugs and method thereof In force · From the USPTO record | In force | From the USPTO record | |
| US 8,588,357 | Phase selector capable of tolerating jitter and method thereof, and clock and data recovery circuit In force · From the USPTO record | In force | From the USPTO record | |
| US 8,675,799 | Circuit for generating a clock data recovery phase locked indicator and method thereof In force · From the USPTO record | In force | From the USPTO record | |
| US 8,767,759 | Method of reducing required capacity of retry buffer for real-time transfer through PCIe and related device In force · From the USPTO record | In force | From the USPTO record | |
| US 9,372,528 | Universal serial bus (USB) 3.0 compatible host with lower operation power consumption and method for reducing operation power consumption of a USB 3.0 compatible host In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 21: 1 lapsed for an unpaid fee. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
Every application published under this name has become a patent.