Gray Research LLC
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
0
Ending by 2030
Dec 2035
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Mar 17, 2027The maintenance fee for Connecting diverse client cores using a directional two-dimensional router and network (US 10,419,338) comes due Mar 17, 2027. Unpaid by Sep 17, 2027, it lapses early.
- 1 fee due Sep 10, 2027The maintenance fee for Composing Cores and FPGAs at Massive Scale with Directional, Two Dimensional Routers and Interconnection Networks (US 10,587,534) comes due Sep 10, 2027. Unpaid by Mar 10, 2028, it lapses early.
- 1 fee due Oct 30, 2027The maintenance fee for Composing Diverse Remote Cores and FPGAs (US 11,973,697) comes due Oct 30, 2027. Unpaid by May 1, 2028, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
Showing 1 to 8 of 8
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 10,419,338 | Connecting diverse client cores using a directional two-dimensional router and network In force · From the USPTO record | In force | From the USPTO record | |
| US 10,911,352 | Multicast message delivery using a directional two-dimensional router and network In force · From the USPTO record | In force | From the USPTO record | |
| US 10,116,557 | Directional two-dimensional router and interconnection network for field programmable gate arrays, and other circuits and applications of the router and network In force · From the USPTO record | In force | From the USPTO record | |
| US 11,677,662 | FPGA-Efficient Directional Two-Dimensional Router In force · Low confidence | In force | Low confidence | |
| US 10,587,534 | Composing Cores and FPGAs at Massive Scale with Directional, Two Dimensional Routers and Interconnection Networks In force · High confidence | In force | High confidence | |
| US 11,973,697 | Composing Diverse Remote Cores and FPGAs In force · High confidence | In force | High confidence | |
| US 11,223,573 | Shortcut Routing on Segmented Directional Torus Interconnection Networks In force · High confidence | In force | High confidence | |
| US 11,455,171 | Multiported parity scoreboard circuit In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 8: 1 lapsed for an unpaid fee. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
1 pending · 1 no status recorded