Kinsus Interconnect Technology Corp.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
9
Ending by 2030
Mar 2027
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Dec 25, 2026The maintenance fee for Multi-layer circuit board capable of being applied with electrical testing and method for manufacturing the same (US 10,334,719) comes due Dec 25, 2026. Unpaid by Jun 25, 2027, it lapses early.
- 3 fees due Jan 28 to 30, 2027 · next Jan 28
- 2 fees due Feb 6 to 13, 2027 · next Feb 6
- 1 fee due Mar 3, 2027The maintenance fee for Multi-layer circuit board (US 10,405,423) comes due Mar 3, 2027. Unpaid by Sep 3, 2027, it lapses early.
- 3 fees due Apr 8 to 22, 2027 · next Apr 8
- 1 fee due May 24, 2027The maintenance fee for Double sided board with buried element and method for manufacturing the same (US 9,198,296) comes due May 24, 2027. Unpaid by Nov 24, 2027, it lapses early.
- 1 fee due Sep 29, 2027The maintenance fee for Method for manufacturing microthrough-hole in circuit board and circuit board structure with microthrough-hole (US 9,301,405) comes due Sep 29, 2027. Unpaid by Mar 29, 2028, it lapses early.
Recent changes
- 3 of the patents on this record were granted since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 7,405,146 | Electroplating method by transmitting electric current from a ball side In force · From the USPTO record | In force | From the USPTO record | |
| US 7,488,675 | Method for fabricating IC board without ring structure In force · From the USPTO record | In force | From the USPTO record | |
| US 7,573,721 | Embedded passive device structure and manufacturing method thereof In force · From the USPTO record | In force | From the USPTO record | |
| US 8,186,054 | Method of fabricating board having high density core layer and structure thereof In force · From the USPTO record | In force | From the USPTO record | |
| US 8,051,558 | Manufacturing method of the embedded passive device In force · From the USPTO record | In force | From the USPTO record | |
| US 7,807,034 | Manufacturing method of non-etched circuit board In force · From the USPTO record | In force | From the USPTO record | |
| US 7,871,892 | Method for fabricating buried capacitor structure In force · From the USPTO record | In force | From the USPTO record | |
| US 8,083,954 | Method for fabricating component-embedded printed circuit board In force · From the USPTO record | In force | From the USPTO record | |
| US 8,161,639 | Method for fabricating an interlayer conducting structure of an embedded circuitry In force · From the USPTO record | In force | From the USPTO record | |
| US 8,377,815 | Manufacturing method of a semiconductor load board In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 54: 12 lapsed for an unpaid fee · 2 ended at full term. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
3 pending · 15 no status recorded