Mips Tech, LLC
8 more in force are now held by other companies
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
Previously recorded as Hellosoft, Inc. (to 2018)
19
Ending by 2030
Dec 2026
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 3 fees due Dec 11, 2026
- 4 fees due Jan 21 to 23, 2027 · next Jan 21
- 2 fees due Feb 6 to 13, 2027 · next Feb 6
- 3 fees due Mar 8 to 24, 2027 · next Mar 8
- 1 fee due Apr 29, 2027The maintenance fee for Execution of Load Instructions in a Processor (US 10,459,725) comes due Apr 29, 2027. Unpaid by Oct 29, 2027, it lapses early.
- 3 fees due May 17 to 28, 2027 · next May 17
- 3 fees due Jul 12 to 21, 2027 · next Jul 12
- 2 fees due Aug 6 to 20, 2027 · next Aug 6
- 2 fees due Sep 22 to 29, 2027 · next Sep 22
- 1 fee due Oct 5, 2027The maintenance fee for Register File Having a Plurality of Sub-Register Files (US 9,304,934) comes due Oct 5, 2027. Unpaid by Apr 5, 2028, it lapses early.
- 3 fees due Nov 5 to 12, 2027 · next Nov 5
Recent changes
- 1 of the patents on this record was granted since Aug 16, 2026
- 1 term has ended since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 7,558,939 | Three-Tiered Translation Lookaside Buffer Hierarchy in a Multithreading Microprocessor In force · High confidence | In force | High confidence | |
| US 8,725,950 | Horizontally-Shared Cache Victims in Multiple Core Processors In force · High confidence | In force | High confidence | |
| US 10,437,598 | Method and Apparatus for Selecting Among a Plurality of Instruction Sets to a Microprocessor In force · High confidence | In force | High confidence | |
| US 7,836,450 | Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts In force · Medium confidence | In force | Medium confidence | |
| US 7,849,297 | Software Emulation of Directed Exceptions in a Multithreading Processor In force · Medium confidence | In force | Medium confidence | |
| US 7,870,553 | Symmetric Multiprocessor Operating System for Execution on Non-Independent Lightweight Thread Contexts In force · Medium confidence | In force | Medium confidence | |
| US 7,694,304 | Mechanisms for Dynamic Configuration of Virtual Processor Resources In force · Medium confidence | In force | Medium confidence | |
| US 7,657,891 | Multithreading Microprocessor with Optimized Thread Scheduler for Increasing Pipeline Utilization Efficiency In force · High confidence | In force | High confidence | |
| US 7,774,549 | Horizontally-Shared Cache Victims in Multiple Core Processors In force · High confidence | In force | High confidence | |
| US 7,739,455 | Avoiding Livelock Using a Cache Manager in Multiple Core Processors In force · High confidence | In force | High confidence |
Also on record, not counted in the 103: 8 patents in force now held by others · 37 ended at full term. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
4 no status recorded