Mosys, Inc.
3 more in force are now held by other companies
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
Recorded as renamed to Peraso Inc. (2022)
4
Ending by 2030
Oct 2027
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Nov 19, 2026The maintenance fee for Memory device with background built-in self-testing and background built-in self-repair (US 9,037,928) comes due Nov 19, 2026. Unpaid by May 19, 2027, it lapses early.
- 2 fees due Dec 9 to 11, 2026 · next Dec 9
- 1 fee due Jan 2, 2027The maintenance fee for System and method to match vectors using mask and count (US 10,339,043) comes due Jan 2, 2027. Unpaid by Jul 2, 2027, it lapses early.
- 1 fee due Feb 25, 2027The maintenance fee for Data synchronization for circuit resources without using a resource buffer (US 9,118,611) comes due Feb 25, 2027. Unpaid by Aug 25, 2027, it lapses early.
- 1 fee due Mar 29, 2027The maintenance fee for Delay-locked loop with independent phase adjustment of delayed clock output pairs (US 9,148,154) comes due Mar 29, 2027. Unpaid by Sep 29, 2027, it lapses early.
Recent changes
- 3 terms have ended since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 7,533,222 | Dual-port SRAM memory using single-port memory cell In force · From the USPTO record | In force | From the USPTO record | |
| US 7,599,396 | Method of encoding and synchronizing a serial interface In force · From the USPTO record | In force | From the USPTO record | |
| US 9,030,894 | Hierarchical multi-bank multi-port memory organization In force · From the USPTO record | In force | From the USPTO record | |
| US 8,890,332 | Semiconductor chip layout with staggered Tx and Tx data lines In force · From the USPTO record | In force | From the USPTO record | |
| US 9,118,611 | Data synchronization for circuit resources without using a resource buffer In force · From the USPTO record | In force | From the USPTO record | |
| US 8,901,747 | Semiconductor chip layout In force · From the USPTO record | In force | From the USPTO record | |
| US 9,148,154 | Delay-locked loop with independent phase adjustment of delayed clock output pairs In force · From the USPTO record | In force | From the USPTO record | |
| US 9,037,928 | Memory device with background built-in self-testing and background built-in self-repair In force · From the USPTO record | In force | From the USPTO record | |
| US 8,954,803 | Programmable Test Engine (PCDTE) for Emerging Memory Technologies In force · High confidence | In force | High confidence | |
| US 8,988,956 | Programmable Memory Built in Self Repair Circuit In force · High confidence | In force | High confidence |
Also on record, not counted in the 14: 3 patents in force now held by others · 74 lapsed for an unpaid fee · 77 ended at full term. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
17 no status recorded