Movellus Circuits Incorporated
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
0
Ending by 2030
Jul 2036
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due May 28, 2027The maintenance fee for Frequency multiplier system with multi-transition controller (US 11,831,318) comes due May 28, 2027. Unpaid by Nov 29, 2027, it lapses early.
- 2 fees due Sep 10 to 17, 2027 · next Sep 10
- 1 fee due Oct 7, 2027The maintenance fee for Timing analysis for electronic design automation of parallel multi-state driver circuits (US 10,614,182) comes due Oct 7, 2027. Unpaid by Apr 7, 2028, it lapses early.
- 1 fee due Nov 7, 2027The maintenance fee for Frequency multiplier circuit with programmable frequency transition controller (US 11,979,165) comes due Nov 7, 2027. Unpaid by May 8, 2028, it lapses early.
Recent changes
- 1 of the patents on this record was granted since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 9,680,480 | Fractional and reconfigurable digital phase-locked loop In force · From the USPTO record | In force | From the USPTO record | |
| US 9,698,798 | Digital controller for a phase-locked loop In force · From the USPTO record | In force | From the USPTO record | |
| US 9,705,516 | Reconfigurable phase-locked loop with optional LC oscillator capability In force · From the USPTO record | In force | From the USPTO record | |
| US 9,762,249 | Reconfigurable phase-locked loop In force (reinstated) · From the USPTO record | In force (reinstated) | From the USPTO record | |
| US 10,587,275 | Locked loop circuit with configurable second error input In force · From the USPTO record | In force | From the USPTO record | |
| US 11,017,138 | Timing analysis for parallel multi-state driver circuits In force · From the USPTO record | In force | From the USPTO record | |
| US 10,031,992 | Concurrently optimized system-on-chip implementation with automatic synthesis and integration In force · From the USPTO record | In force | From the USPTO record | |
| US 10,158,365 | Digital, Reconfigurable Frequency and Delay Generator with Phase Measurement In force · High confidence | In force | High confidence | |
| US 10,713,409 | Integrated circuit design system with automatic timing margin reduction In force · From the USPTO record | In force | From the USPTO record | |
| US 10,740,526 | Integrated circuit design system with automatic timing margin reduction In force · From the USPTO record | In force | From the USPTO record |
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
1 no status recorded