PDF Solutions, Inc.
3 more in force are now held by other companies
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
Recorded under 2 name spellings.
10
Ending by 2030
Jan 2027
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 2 fees due Dec 6 to 27, 2026 · next Dec 6
- 1 fee due Feb 13, 2027The maintenance fee for Direct probing characterization vehicle for transistor, capacitor and resistor testing (US 10,380,305) comes due Feb 13, 2027. Unpaid by Aug 13, 2027, it lapses early.
- 2 fees due Mar 10 to 19, 2027 · next Mar 10
- 2 fees due Apr 1 to 3, 2027 · next Apr 1
- 1 fee due Jun 24, 2027The maintenance fee for Characterization vehicles for printed circuit board and system design (US 10,517,169) comes due Jun 24, 2027. Unpaid by Dec 27, 2027, it lapses early.
- 1 fee due Jul 7, 2027The maintenance fee for Test structures and method for electrical measurement of FinFET fin height (US 10,529,631) comes due Jul 7, 2027. Unpaid by Jan 7, 2028, it lapses early.
- 1 fee due Aug 18, 2027The maintenance fee for Standard cell design conformance using boolean assertions (US 10,565,344) comes due Aug 18, 2027. Unpaid by Feb 18, 2028, it lapses early.
- 1 fee due Sep 17, 2027The maintenance fee for Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (US 10,593,604) comes due Sep 17, 2027. Unpaid by Mar 17, 2028, it lapses early.
- 3 fees due Oct 14 to 30, 2027 · next Oct 14
- 2 fees due Nov 5, 2027
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 8,082,529 | Method and system for mapping a boolean logic network to a limited set of application-domain specific logic cells In force (reinstated) · From the USPTO record | In force (reinstated) | From the USPTO record | |
| US 7,592,827 | Apparatus and method for electrical detection and localization of shorts in metal interconnect lines In force · From the USPTO record | In force | From the USPTO record | |
| US 7,827,516 | Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns In force · From the USPTO record | In force | From the USPTO record | |
| US 7,494,893 | Identifying yield-relevant process parameters in integrated circuit device fabrication processes In force (reinstated) · From the USPTO record | In force (reinstated) | From the USPTO record | |
| US 7,739,065 | Inspection plan optimization based on layout attributes and process variance In force · From the USPTO record | In force | From the USPTO record | |
| US 7,644,388 | Method for reducing layout printability effects on semiconductor device performance In force · From the USPTO record | In force | From the USPTO record | |
| US 8,037,379 | Prediction of impact on post-repair yield resulting from manufacturing process modification In force · From the USPTO record | In force | From the USPTO record | |
| US 8,901,951 | High Density Test Structure Array to Support Addressable High Accuracy 4-Terminal Measurements In force (reinstated) · Medium confidence | In force (reinstated) | Medium confidence | |
| US 7,969,199 | Pattern controlled IC layout In force · From the USPTO record | In force | From the USPTO record | |
| US 8,004,315 | Process for making and designing an IC with pattern controlled layout regions In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 56: 3 patents in force now held by others · 126 lapsed for an unpaid fee · 21 ended at full term. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
4 pending · 2 abandoned · 6 no status recorded