Piecemakers Technology, Inc.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
Recorded under 2 name spellings.
0
Ending by 2030
Feb 2033
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Feb 8, 2027The maintenance fee for DRAM with inter-section, page-data-copy scheme for low power and wide data access (US 11,721,390) comes due Feb 8, 2027. Unpaid by Aug 9, 2027, it lapses early.
- 1 fee due Mar 12, 2027The maintenance fee for Apparatus for data processing in conjunction with memory array access (US 11,755,685) comes due Mar 12, 2027. Unpaid by Sep 13, 2027, it lapses early.
- 1 fee due Aug 11, 2027The maintenance fee for Circuit topology of memory chips with embedded function test pattern generation module connected to normal access port physical layer (US 10,559,374) comes due Aug 11, 2027. Unpaid by Feb 11, 2028, it lapses early.
- 1 fee due Oct 28, 2027The maintenance fee for Method for testing semiconductor die pad untouched by probe and related test circuit (US 10,634,713) comes due Oct 28, 2027. Unpaid by Apr 28, 2028, it lapses early.
Recent changes
- 1 of the patents on this record was granted since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 8,754,656 | High speed test circuit and method In force · From the USPTO record | In force | From the USPTO record | |
| US 9,466,355 | Memory architecture dividing memory cell array into independent memory banks In force · From the USPTO record | In force | From the USPTO record | |
| US 9,679,622 | Method for controlling memory device asynchronously with respect to system clock, and related memory device and memory system In force · From the USPTO record | In force | From the USPTO record | |
| US 9,653,148 | Multi-bank memory device and system In force · From the USPTO record | In force | From the USPTO record | |
| US 9,997,224 | Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank In force · From the USPTO record | In force | From the USPTO record | |
| US 10,559,374 | Circuit topology of memory chips with embedded function test pattern generation module connected to normal access port physical layer In force · From the USPTO record | In force | From the USPTO record | |
| US 10,634,713 | Method for testing semiconductor die pad untouched by probe and related test circuit In force · From the USPTO record | In force | From the USPTO record | |
| US 11,183,231 | Apparatus for enhancing prefetch access in memory module In force · From the USPTO record | In force | From the USPTO record | |
| US 11,437,087 | Method and apparatus for accumulating and storing respective access counts of word lines in memory module In force · From the USPTO record | In force | From the USPTO record | |
| US 11,393,547 | Anti-fuse one-time programmable memory cell and related array structure In force · From the USPTO record | In force | From the USPTO record |
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
1 no status recorded