Proteantecs Ltd.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
0
Ending by 2030
Nov 2038
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Feb 28, 2027The maintenance fee for Integrated Circuit Degradation Estimation and Time-Of-Failure Prediction Using Workload and Margin Sensing (US 11,740,281) comes due Feb 28, 2027. Unpaid by Aug 30, 2027, it lapses early.
- 2 fees due Mar 19, 2027
- 1 fee due May 14, 2027The maintenance fee for Die-to-die connectivity monitoring using a clocked receiver (US 11,815,551) comes due May 14, 2027. Unpaid by Nov 15, 2027, it lapses early.
- 1 fee due Jun 12, 2027The maintenance fee for Integrated circuit margin measurement and failure prediction device (US 11,841,395) comes due Jun 12, 2027. Unpaid by Dec 13, 2027, it lapses early.
- 1 fee due Sep 12, 2027The maintenance fee for Memory device degradation monitoring (US 11,929,131) comes due Sep 12, 2027. Unpaid by Mar 13, 2028, it lapses early.
Recent changes
- 1 of the patents on this record was granted since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 11,841,395 | Integrated circuit margin measurement and failure prediction device In force · From the USPTO record | In force | From the USPTO record | |
| US 12,535,521 | Integrated Circuit Margin Measurement and Failure Prediction Device In force · Medium confidence | In force | Medium confidence | |
| US 11,740,281 | Integrated Circuit Degradation Estimation and Time-Of-Failure Prediction Using Workload and Margin Sensing In force · High confidence | In force | High confidence | |
| US 12,092,684 | Integrated Circuit Workload, Temperature, And/Or Sub-Threshold Leakage Sensor In force · Medium confidence | In force | Medium confidence | |
| US 12,282,058 | Integrated circuit pad failure detection In force · From the USPTO record | In force | From the USPTO record | |
| US 11,391,771 | Integrated Circuit Pad Failure Detection In force · High confidence | In force | High confidence | |
| US 12,320,844 | Integrated Circuit Profiling and Anomaly Detection In force · High confidence | In force | High confidence | |
| US 11,408,932 | Integrated Circuit Workload, Temperature And/Or Subthreshold Leakage Sensor In force · High confidence | In force | High confidence | |
| US 11,132,485 | Efficient integrated circuit simulation and testing In force · From the USPTO record | In force | From the USPTO record | |
| US 12,216,976 | Efficient integrated circuit simulation and testing In force · From the USPTO record | In force | From the USPTO record |
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
5 pending · 4 no status recorded