PseudolithIC, Inc.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
0
Ending by 2030
Jan 2043
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Feb 22, 2027The maintenance fee for Built in self-test of heterogeneous integrated radio frequency chiplets (US 11,733,297) comes due Feb 22, 2027. Unpaid by Aug 23, 2027, it lapses early.
- 1 fee due Mar 12, 2027The maintenance fee for Chip integration into cavities of a host wafer using lateral dielectric material bonding (US 11,756,848) comes due Mar 12, 2027. Unpaid by Sep 13, 2027, it lapses early.
- 1 fee due May 7, 2027The maintenance fee for Heterogeneous Integration of Radio Frequency Transistor Chiplets Having Interconnection Tuning Circuits (US 11,810,876) comes due May 7, 2027. Unpaid by Nov 8, 2027, it lapses early.
- 1 fee due Sep 26, 2027The maintenance fee for Built in Self-Test of Heterogeneous Integrated Radio Frequency Chiplets (US 11,940,495) comes due Sep 26, 2027. Unpaid by Mar 27, 2028, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
Showing 1 to 10 of 10
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 11,756,848 | Chip integration into cavities of a host wafer using lateral dielectric material bonding In force · From the USPTO record | In force | From the USPTO record | |
| US 12,125,759 | Chip Integration into Cavities of a Host Wafer Using Lateral Dielectric Material Bonding In force · Low confidence | In force | Low confidence | |
| US 12,261,091 | Chip Integration into Cavities of a Host Wafer Using Lateral Dielectric Material Bonding In force · Medium confidence | In force | Medium confidence | |
| US 11,810,876 | Heterogeneous Integration of Radio Frequency Transistor Chiplets Having Interconnection Tuning Circuits In force · High confidence | In force | High confidence | |
| US 12,322,714 | Heterogeneous Integration of Radio Frequency Transistor Chiplets Having Interconnection Tuning Circuits In force · High confidence | In force | High confidence | |
| US 11,733,297 | Built in self-test of heterogeneous integrated radio frequency chiplets In force · From the USPTO record | In force | From the USPTO record | |
| US 11,940,495 | Built in Self-Test of Heterogeneous Integrated Radio Frequency Chiplets In force · Medium confidence | In force | Medium confidence | |
| US 12,099,092 | Built in Self-Test of Heterogeneous Integrated Radio Frequency Chiplets In force · Low confidence | In force | Low confidence | |
| US 12,191,295 | Heterogeneous Integration of Radio Frequency Transistor Chiplets Having Interconnections to Host Wafer Circuits for Optimizing Operating Conditions In force · High confidence | In force | High confidence | |
| US 12,658,854 | Dual-Polarization and Dual-Band Radio Frequency (RF) Transceivers with Leakage and Image Rejection Calibration In force · High confidence | In force | High confidence |
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
5 pending