Sdep Corp.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
5
Ending by 2030
Oct 2030
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Jan 14, 2027The maintenance fee for Memory and process sharing via input/output with virtualization (US 9,081,766) comes due Jan 14, 2027. Unpaid by Jul 14, 2027, it lapses early.
- 1 fee due Apr 27, 2027The maintenance fee for Leakage and performance graded memory (US 9,171,846) comes due Apr 27, 2027. Unpaid by Oct 27, 2027, it lapses early.
- 2 fees due May 17, 2027
- 1 fee due Oct 19, 2027The maintenance fee for Active memory processor system (US 9,317,437) comes due Oct 19, 2027. Unpaid by Apr 19, 2028, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 8,200,942 | Hybrid multifunction component system with component interface encapsulation including OS packet translator for communication over unified data bus architecture In force · From the USPTO record | In force | From the USPTO record | |
| US 8,874,847 | Active Memory Processor System In force · Medium confidence | In force | Medium confidence | |
| US 9,317,437 | Active memory processor system In force · From the USPTO record | In force | From the USPTO record | |
| US 9,348,756 | Active memory processor system In force · From the USPTO record | In force | From the USPTO record | |
| US 9,189,400 | Hybrid active memory processor system In force · From the USPTO record | In force | From the USPTO record | |
| US 9,190,371 | Self-organizing network with chip package having multiple interconnection configurations In force · From the USPTO record | In force | From the USPTO record | |
| US 8,935,143 | Semiconductor Sensor Reliability In force · High confidence | In force | High confidence | |
| US 9,081,766 | Memory and process sharing via input/output with virtualization In force · From the USPTO record | In force | From the USPTO record | |
| US 8,886,969 | Input/Output Device Power Reduction and Optimization by Enablement or Disablement of an External Circuit Coupled to the Input/Output Device In force · High confidence | In force | High confidence | |
| US 9,171,846 | Leakage and performance graded memory In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 11: 7 lapsed for an unpaid fee. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.