Silex Microsystems AB
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
Recorded under 2 name spellings.
16
Ending by 2030
Dec 2026
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Jun 29, 2027The maintenance fee for CTE matched interposer and method of making (US 9,224,681) comes due Jun 29, 2027. Unpaid by Dec 29, 2027, it lapses early.
- 1 fee due Jul 19, 2027The maintenance fee for Semiconductor devices with close-packed via structures having in-plane routing and method of making same (US 9,240,373) comes due Jul 19, 2027. Unpaid by Jan 19, 2028, it lapses early.
- 1 fee due Aug 2, 2027The maintenance fee for Starting substrate for semiconductor engineering having substrate-through connections and a method for making same (US 9,249,009) comes due Aug 2, 2027. Unpaid by Feb 2, 2028, it lapses early.
- 1 fee due Oct 12, 2027The maintenance fee for Methods for making a starting substrate wafer for semiconductor engineering having wafer through connections (US 9,312,217) comes due Oct 12, 2027. Unpaid by Apr 12, 2028, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 8,637,351 | Methods for making micro needles and applications thereof In force · From the USPTO record | In force | From the USPTO record | |
| US 8,598,676 | Barrier Structure In force · High confidence | In force | High confidence | |
| US 8,871,641 | Low resistance through-wafer via In force · From the USPTO record | In force | From the USPTO record | |
| US 8,324,103 | Vias and method of making In force · From the USPTO record | In force | From the USPTO record | |
| US 8,308,960 | Methods for making micro needles and applications thereof In force · From the USPTO record | In force | From the USPTO record | |
| US 9,312,217 | Methods for making a starting substrate wafer for semiconductor engineering having wafer through connections In force · From the USPTO record | In force | From the USPTO record | |
| US 8,338,957 | Low resistance through-wafer via In force · From the USPTO record | In force | From the USPTO record | |
| US 8,742,588 | Method for making via interconnection In force · From the USPTO record | In force | From the USPTO record | |
| US 9,620,390 | Method of making a semiconductor device having a functional capping In force · From the USPTO record | In force | From the USPTO record | |
| US 8,630,033 | Via structure and method thereof In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 29: 8 ended at full term. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
2 abandoned · 2 no status recorded