Simplex Micro, Inc.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
0
Ending by 2030
Jan 2042
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 3 fees due May 28, 2027
- 1 fee due Oct 9, 2027The maintenance fee for Multi-threading microprocessor with a time counter for statically dispatching instructions (US 11,954,491) comes due Oct 9, 2027. Unpaid by Apr 10, 2028, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 11,954,491 | Multi-threading microprocessor with a time counter for statically dispatching instructions In force · From the USPTO record | In force | From the USPTO record | |
| US 11,829,187 | Microprocessor with Time Counter for Statically Dispatching Instructions In force · High confidence | In force | High confidence | |
| US 11,829,762 | Time-resource matrix for a microprocessor with time counter for statically dispatching instructions In force · From the USPTO record | In force | From the USPTO record | |
| US 11,829,767 | Register scoreboard for a microprocessor with a time counter for statically dispatching instructions In force · From the USPTO record | In force | From the USPTO record | |
| US 12,190,116 | Microprocessor with time count based instruction execution and replay In force · From the USPTO record | In force | From the USPTO record | |
| US 12,141,580 | Microprocessor with non-cacheable memory load prediction In force · From the USPTO record | In force | From the USPTO record | |
| US 12,443,412 | Method and apparatus for a scalable microprocessor with time counter In force · From the USPTO record | In force | From the USPTO record | |
| US 12,112,172 | Vector coprocessor with time counter for statically dispatching instructions In force · From the USPTO record | In force | From the USPTO record | |
| US 12,106,114 | Microprocessor with shared read and write buses and instruction issuance to multiple register sets in accordance with a time counter In force · From the USPTO record | In force | From the USPTO record | |
| US 12,001,848 | Microprocessor with time counter for statically dispatching instructions with phantom registers In force · From the USPTO record | In force | From the USPTO record |
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
1 abandoned · 1 no status recorded
Showing 1 to 2 of 2, newest filing first. An application has no patent term. A term is computed when and if it grants, and appears on that patent's own page. Where no title is shown, the bulk publication record carries none and this site holds no USPTO file history for that application.
| Application | Title | Filed | Status |
|---|---|---|---|
| 19/074,788 | Mar 10, 2025 | No status recorded | |
| 18/603,171 | Apparatus and Method for Implementing Many Different Loop Types in a Microprocessor | Mar 12, 2024 | Abandoned |