TC Lab, Inc.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
0
Ending by 2030
Jan 2035
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Mar 19, 2027The maintenance fee for 3D memory array clusters and resulting memory architecture (US 11,763,872) comes due Mar 19, 2027. Unpaid by Sep 20, 2027, it lapses early.
- 1 fee due Apr 29, 2027The maintenance fee for Methods of reading and writing data in a thyristor random access memory (US 10,460,789) comes due Apr 29, 2027. Unpaid by Oct 29, 2027, it lapses early.
- 2 fees due Jul 7 to 14, 2027 · next Jul 7
- 3 fees due Aug 4 to 25, 2027 · next Aug 4
- 1 fee due Oct 28, 2027The maintenance fee for 3D stacked high-density memory cell arrays and methods of manufacture (US 10,636,473) comes due Oct 28, 2027. Unpaid by Apr 28, 2028, it lapses early.
Recent changes
Nothing was recorded against this company's patents in the last 90 days.
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 9,564,199 | Methods of Reading and Writing Data in a Thyristor Random Access Memory In force · High confidence | In force | High confidence | |
| US 9,899,389 | Two-Transistor SRAM Semiconductor Structure and Methods of Fabrication In force · High confidence | In force | High confidence | |
| US 10,020,043 | Methods of Reading and Writing Data in a Thyristor Random Access Memory In force · High confidence | In force | High confidence | |
| US 10,460,789 | Methods of reading and writing data in a thyristor random access memory In force · From the USPTO record | In force | From the USPTO record | |
| US 10,529,718 | Thyristor volatile random access memory and methods of manufacture In force · From the USPTO record | In force | From the USPTO record | |
| US 10,553,588 | Thyristor volatile random access memory and methods of manufacture In force · From the USPTO record | In force | From the USPTO record | |
| US 9,842,639 | Systems and Methods for Managing Read Voltages in a Cross-Point Memory Array In force · High confidence | In force | High confidence | |
| US 10,032,500 | Memory Disturb Recovery Scheme for Cross-Point Memory Arrays In force · High confidence | In force | High confidence | |
| US 9,899,390 | Methods and Systems for Reducing Electrical Disturb Effects Between Thyristor Memory Cells Using Heterostructured Cathodes In force · High confidence | In force | High confidence | |
| US 10,535,657 | High Density Vertical Thyristor Memory Cell Array with Improved Isolation In force · High confidence | In force | High confidence |
Also on record, not counted in the 26: 24 lapsed for an unpaid fee. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
4 no status recorded