Worldwide Pro Ltd.
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
10
Ending by 2030
Feb 2027
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 1 fee due Jan 30, 2027The maintenance fee for Using a Barycenter compact model for a circuit network (US 10,366,195) comes due Jan 30, 2027. Unpaid by Jul 30, 2027, it lapses early.
- 1 fee due Aug 11, 2027The maintenance fee for Partitioning a system graph for circuit simulation to obtain an exact solution (US 10,558,772) comes due Aug 11, 2027. Unpaid by Feb 11, 2028, it lapses early.
- 1 fee due Sep 15, 2027The maintenance fee for Hierarchical visualization-based analysis of integrated circuits (US 9,286,430) comes due Sep 15, 2027. Unpaid by Mar 15, 2028, it lapses early.
Recent changes
- 1 term has ended since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 8,396,696 | Using multiple processors to simulate electronic circuits In force · From the USPTO record | In force | From the USPTO record | |
| US 8,738,335 | Solving a circuit network in hierarchical, multicore, and distributed computing environment In force · From the USPTO record | In force | From the USPTO record | |
| US 7,461,360 | Validating very large network simulation results In force · From the USPTO record | In force | From the USPTO record | |
| US 10,140,396 | Partitioning electronic circuits for simulation on multiple processors In force · From the USPTO record | In force | From the USPTO record | |
| US 8,694,302 | Solving a hierarchical circuit network using a Barycenter compact model In force · From the USPTO record | In force | From the USPTO record | |
| US 8,166,425 | Validating circuit simulation results In force · From the USPTO record | In force | From the USPTO record | |
| US 10,366,195 | Using a Barycenter compact model for a circuit network In force · From the USPTO record | In force | From the USPTO record | |
| US 10,558,772 | Partitioning a system graph for circuit simulation to obtain an exact solution In force · From the USPTO record | In force | From the USPTO record | |
| US 7,827,016 | Simulating circuits by distributed computing In force · From the USPTO record | In force | From the USPTO record | |
| US 8,112,264 | Simulating circuits using network tearing In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 18: 15 ended at full term. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
Every application published under this name has become a patent.