Powertech Technology Inc.
1 more in force is now held by another company
Held is read from USPTO's recorded assignments; a transfer never recorded there does not appear.
Recorded under 2 name spellings.
11
Ending by 2030
Nov 2028
Next term end
When these terms end
Held patents by the year their term ends
20262027202820292030203120322033203420352036203720382039204020412042204320442045
Fee deadlines
Maintenance fees fall due 3.5, 7.5 and 11.5 years after grant. A missed fee ends a patent at the end of the six month grace period that follows, not on the due date.
- 4 fees due Dec 6 to 25, 2026 · next Dec 6
- 2 fees due Jan 4, 2027
- 2 fees due Feb 13 to 20, 2027 · next Feb 13
- 1 fee due Mar 26, 2027The maintenance fee for Package structure and manufacturing method thereof (US 11,769,763) comes due Mar 26, 2027. Unpaid by Sep 27, 2027, it lapses early.
- 3 fees due Apr 1 to 29, 2027 · next Apr 1
- 3 fees due Jun 19 to 30, 2027 · next Jun 19
- 2 fees due Aug 2 to 27, 2027 · next Aug 2
- 4 fees due Sep 17 to 30, 2027 · next Sep 17
- 5 fees due Oct 7 to 30, 2027 · next Oct 7
Recent changes
- 1 of the patents on this record was granted since Aug 16, 2026
Patents held now
Soonest term end first. Each date below is computed on that patent's own page, which shows the rule, the adjustments and the fee history it was derived from.
| Patent | Title | Status | Expires | Confidence |
|---|---|---|---|---|
| US 7,569,935 | Pillar-to-pillar flip-chip assembly In force · From the USPTO record | In force | From the USPTO record | |
| US 7,776,649 | Method for fabricating wafer level chip scale packages In force · From the USPTO record | In force | From the USPTO record | |
| US 7,812,430 | Leadframe and semiconductor package having downset baffle paddles In force · From the USPTO record | In force | From the USPTO record | |
| US 7,972,904 | Wafer level packaging method In force · From the USPTO record | In force | From the USPTO record | |
| US 7,985,662 | Method for manufacturing dies formed with a dielectric layer In force · From the USPTO record | In force | From the USPTO record | |
| US 7,927,919 | Semiconductor packaging method to save interposer In force · From the USPTO record | In force | From the USPTO record | |
| US 8,040,690 | Inner-connecting structure of lead frame and its connecting method In force · From the USPTO record | In force | From the USPTO record | |
| US 8,063,492 | Multi-chip stacked package In force · From the USPTO record | In force | From the USPTO record | |
| US 8,049,339 | Semiconductor package having isolated inner lead In force · From the USPTO record | In force | From the USPTO record | |
| US 8,125,063 | COL package having small chip hidden between leads In force · From the USPTO record | In force | From the USPTO record |
Also on record, not counted in the 137: 1 patent in force now held by others · 71 lapsed for an unpaid fee. List them
Sources and methods
Compiled from the USPTO record, grants, published applications and recorded assignments, not yet reviewed by hand.
How this record was built
Computed patent terms end on the dates shown. Related patents and pending applications may cover overlapping subject matter.
Published applications
US patent applications published under this name that have not become patents. An application is published about eighteen months after its earliest filing; one that has not been published is in no public record.
11 pending · 1 abandoned · 120 no status recorded