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Powertech Technology Inc.

Also on record
Records under this name other than the patents Powertech Technology Inc. holds now: patents now held by others, patents whose terms have ended, and its applications, pending or abandoned. None of them is counted in the 137 patents it holds.

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PatentTitleStatus Expires Confidence
US 9,761,568Thin fan-out multi-chip stacked packages and the method for manufacturing the same
Formerly held
In force
 · From the USPTO record
In forceFrom the USPTO record
US 9,627,228Method for manufacturing a chip package having a coating layer
Lapsed on the fee record
Ended Apr 18, 2025 · From the USPTO record
Lapsed on the fee recordEnded Apr 18, 2025From the USPTO record
US 8,378,483Fabrication process and device of multi-chip package having spliced substrates
Lapsed on the fee record
Ended Feb 19, 2025 · From the USPTO record
Lapsed on the fee recordEnded Feb 19, 2025From the USPTO record
US 9,553,036Semiconductor package and manufacturing method thereof
Lapsed on the fee record
Ended Jan 24, 2025 · From the USPTO record
Lapsed on the fee recordEnded Jan 24, 2025From the USPTO record
US 8,237,273Metal post chip connecting device and method free to use soldering material
Lapsed on the fee record
Ended Aug 7, 2024 · From the USPTO record
Lapsed on the fee recordEnded Aug 7, 2024From the USPTO record
US 8,212,349Semiconductor package having chip using copper process
Lapsed on the fee record
Ended Jul 3, 2024 · From the USPTO record
Lapsed on the fee recordEnded Jul 3, 2024From the USPTO record
US 10,424,526Chip package structure and manufacturing method thereof
Lapsed on the fee record
Ended Sep 24, 2023 · From the USPTO record
Lapsed on the fee recordEnded Sep 24, 2023From the USPTO record
US 9,099,364MPS-C2 semiconductor device having shorter supporting posts
Lapsed on the fee record
Ended Aug 4, 2023 · From the USPTO record
Lapsed on the fee recordEnded Aug 4, 2023From the USPTO record
US 10,354,978Stacked package including exterior conductive element and a manufacturing method of the same
Lapsed on the fee record
Ended Jul 16, 2023 · From the USPTO record
Lapsed on the fee recordEnded Jul 16, 2023From the USPTO record
US 10,276,553Chip package structure and manufacturing method thereof
Lapsed on the fee record
Ended Apr 30, 2023 · From the USPTO record
Lapsed on the fee recordEnded Apr 30, 2023From the USPTO record
10 of 72 patents shown.
Pro members see all 72.
Pro members: see all 72 patents
The Patent Finder CompaniesExpirationsCalculatorWatchlistPricing MethodologyCorrectionsLegalPrivacysupport@thepatentfinder.com Updated Nov 14, 2026 · includes USPTO assignment & status data published Nov 14, 2026 and grant & fee data published Nov 10, 2026 (weekly) Part of 137 Finder · © 2026 137 Finder LLC · Sources cited